Lucas-Belucci-Bellini
@Lucas-Belucci-Bellini
Public Skills
a11y-table-header-scope-audit
by Lucas-Belucci-Bellini
"Audits and verifies a11y table header scope audit with explicit acceptance checks and recoverable failure handling. Use when implementation, configuration, release, or incident evidence must be reviewed for this boundary."
radar-signal-processing-units-and-db-audit
by Lucas-Belucci-Bellini
"Apply deterministic engineering checks to keep amplitude, power, frequency, time, and decibel conventions explicit across code, plots, and report tables."
radar-fan-control-hysteresis-validation
by Lucas-Belucci-Bellini
"Apply deterministic engineering checks to test cooling control hysteresis and fail-safe response to missing temperature telemetry."
radar-chirp-frequency-table-integrity
by Lucas-Belucci-Bellini
"Apply deterministic engineering checks to ensure chirp lookup-table content, dimensions, format, and generated checksums remain reproducible across builds."
radar-frequency-synth-config-review
by Lucas-Belucci-Bellini
"Apply deterministic engineering checks to verify clock and synthesizer configuration tables are complete, revisioned, and rejected when fields are unsupported."
radar-cfar-threshold-synthetic-noise-validation
by Lucas-Belucci-Bellini
"Apply deterministic engineering checks to test adaptive-threshold code with synthetic noise fixtures to verify numeric bounds, edge handling, and stable false-alarm accounting."
radar-doppler-fft-axis-contract
by Lucas-Belucci-Bellini
"Apply deterministic engineering checks to ensure FFT bin ordering, sample interval, units, and zero-bin conventions are documented consistently across FPGA and Python tools."
radar-cic-filter-growth-and-rounding
by Lucas-Belucci-Bellini
"Apply deterministic engineering checks to audit CIC accumulator growth, comb delay, and quantization rounding under worst-case bounded synthetic inputs."
radar-live-data-vs-synthetic-fixture-labeling
by Lucas-Belucci-Bellini
"Apply deterministic engineering checks to prevent generated waveform, test CSV, and software-model output from being confused with hardware captures."
radar-baseband-decimation-alias-rejection
by Lucas-Belucci-Bellini
"Apply deterministic engineering checks to validate baseband decimation configuration and alias rejection using synthetic signals and explicit output-rate metadata."
radar-synthesis-constraint-coverage
by Lucas-Belucci-Bellini
"Apply deterministic engineering checks to check that all required clocks, input/output delays, and timing exceptions are documented and applied to the active design."
radar-fpga-interface-version-compatibility
by Lucas-Belucci-Bellini
"Apply deterministic engineering checks to check compatibility between FPGA bitstream metadata and the STM32/GUI command schema before integration."
radar-firmware-version-skew-matrix
by Lucas-Belucci-Bellini
"Apply deterministic engineering checks to verify the supported version combinations for GUI, MCU firmware, FPGA bitstream, and board hardware."
radar-safe-rf-lab-test-conditions
by Lucas-Belucci-Bellini
"Apply deterministic engineering checks to create a stop/go checklist for any authorized lab test that includes permitted frequency/power, shielded or terminated setup, qualified supervision, and emergency stop readiness."
radar-logging-no-sensitive-data-contract
by Lucas-Belucci-Bellini
"Apply deterministic engineering checks to keep diagnostic logs useful while excluding private coordinates, secrets, and detailed operational traces not needed for debugging."
radar-calibration-record-provenance
by Lucas-Belucci-Bellini
"Apply deterministic engineering checks to track calibration date, instrument, revision, operator, and uncertainty for software that consumes calibration values."
radar-hardware-source-license-compliance
by Lucas-Belucci-Bellini
"Apply deterministic engineering checks to keep CERN-OHL-P hardware-design obligations distinct from MIT software/firmware notices and third-party component documentation."
radar-cross-layer-invariant-test-plan
by Lucas-Belucci-Bellini
"Apply deterministic engineering checks to map shared invariants across Python GUI, STM32, and FPGA so version and state mismatches are tested deliberately."
radar-command-acknowledgment-timeout
by Lucas-Belucci-Bellini
"Apply deterministic engineering checks to specify command acknowledgement and timeout behavior between GUI, STM32, and FPGA without indefinite waits."
radar-peripheral-initialization-order
by Lucas-Belucci-Bellini
"Apply deterministic engineering checks to document and validate dependency ordering for clocks, synthesizers, ADC/DAC devices, FPGA, and sensor interfaces."
radar-iq-component-normalization
by Lucas-Belucci-Bellini
"Apply deterministic engineering checks to verify the I/Q data convention, scaling, sign, and channel ordering at the baseband interface."
radar-antenna-simulated-measurement-parity
by Lucas-Belucci-Bellini
"Apply deterministic engineering checks to compare antenna simulation setup, geometry, material parameters, and measured evidence labels without conflating the two."
radar-rtl-opcode-source-of-truth
by Lucas-Belucci-Bellini
"Apply deterministic engineering checks to keep RTL command and opcode values aligned with the authoritative top-level contract and all dependent interfaces."
radar-rf-switch-state-safety
by Lucas-Belucci-Bellini
"Apply deterministic engineering checks to audit RF switch control transitions for legal states, initialization defaults, and safe behavior after MCU or FPGA failure."