hdldiagzero
by lcapossio
Generate clean SVG block diagrams of HDL / RTL top-level designs. Use whenever the user asks to draw, diagram, sketch, render, or visualize an RTL / HDL / FPGA / SoC design — including phrases like "draw the top-level RTL", "diagram of the SoC", "block diagram", "make an SVG of the design", "visualize the architecture". Applies to Verilog, SystemVerilog, VHDL, Vivado BD, and LiteX projects. Color-codes by clock domain, distinguishes AXI-MM / AXI-Lite / AXI-Stream, omits clock/reset/JTAG/debug.